1. Field of the Invention
The present invention relates to a data processing apparatus and method for handling transactions issued to a slave device from a master device.
2. Description of the Prior Art
In a data processing system in which transactions are issued from master devices to slave devices, a controller is often provided in association with a slave device to handle transactions issued to that slave device by one or more master devices. Each transaction typically involves the transfer of one or more data packets between the master device and the slave device, and depending upon the type of transaction the transfer of data packets may occur in either or both directions between the master device and the slave device.
For example, for a write transaction, a number of data packets will be transferred from the master device to the slave device via the controller, with the number of data packets depending on the burst size of the data being written. Each packet will typically include command data (in this case identifying that the transfer is a write transfer) and any associated data (in this case the data to be written), and the size of each data packet may be fixed or configurable. For example, depending on the width of the bus interconnecting the master and slave devices, the data packets may be 32 bits, 64 bits, 128 bits, etc in length.
Similarly, for a read transaction, there will typically be a data packet transferred from the master device to the slave device to initiate the read operation, followed by one or more data packets transferred from the slave device back to the master device incorporating the required data.
Typically, the controller associated with the slave device is arranged to buffer the data packets that it receives within a buffer storage of the controller, this buffer storage typically being arranged as a First-In-First-Out (FIFO) storage. This FIFO storage is typically used to enable signals to be synchronised between the slave device and the controller clock domain, and to aim to optimise the data transfer rate between the controller and the system memory. The system memory may be any memory area that the master device can access, for example cache, on-chip memory, external memory, etc. In one particular example, the slave device may be a removable memory device, and the master device is a digital signal processor (DSP) or Micro Processing Unit (MPU), with the data retrieved from the removable memory device being stored in system memory accessible by the DSP/MPU.
Due to cost and size considerations, it is desirable that the structure of the controller for the slave device is kept as small and simplified as possible. This typically dictates that a single FIFO structure is provided to perform buffering within the controller. This imposes a number of constraints on the transfer of data packets between the master and slave devices. In particular, it is not possible to change the data direction until the FIFO is empty. Hence, whilst the FIFO contains data packets being transferred from the master device to the slave device, it is not possible for the slave device to return data packets for routing to the master device.
Another issue is that of handling high priority transactions. Typically, the controller has no mechanism for prioritising between transactions, and each transaction is treated equally with its data packets merely being placed in the FIFO storage so that those data packets are transferred in temporal order. This means that if an interrupt command is issued to the slave device, the associated data packet is queued in the FIFO and is then not executed until it reaches the head of the FIFO and can be routed onto the slave device. This clearly imposes a delay in handling the interrupt command.
Considering as an example of the slave device a flash-based removable memory device, such constraints have typically been considered acceptable, since the page unit size of the memory has been relatively small, and hence the number of data packets involved in any particular transaction has been relatively low. However, it is likely that as flash technology develops this will cause the page unit size to increase, which means that the potential latency before high priority commands such as interrupt commands are processed, or before data direction can be changed, becomes longer. Furthermore, the development of flash technology is likely to lead to more complex functional command operations being issued to the slave device, and in such situations the inability to handle transactions differently within the controller may cause unacceptable delays in the handling of certain transactions.
Whilst such delays could be alleviated by the duplication of certain hardware within the controller, so as to provide a number of paths through the controller, this would significantly increase the size and complexity, and hence cost, of the controller.
Accordingly, it would be desirable to improve the handling of transactions within the controller without significantly increasing the cost and complexity of that controller.